We can rewrite the division as x * 1 / y and focus only on implementing 1 / y, the rest is a simple multiplication and we know how to do a VHDL multiplication. In this case, we can map the division values into a ROM / LUT using the divisor number as the address to get the division output value. If we are using modern FPGA, there is an almost simple solution in case the bit number of the divisor number is small, say less than 10/12 bits. If we have timing and area problem, we cannot use this strategy. They are generally demanding in terms of area and they need many clock cycles of execution time. We could also implement division through a cordic. Okay, I understand that dividing for 2 and powers of 2 or for constants is simple,īut if I have to divide by numbers that are not powers of two and are not constant?Īgain, if we use an FPGA the vendor provides IPs that allow division. If we have to compute the division for a constant x / K where K is a constant we can simply calculate the multiplication In this case, we need to distinguish if the number is constant or no-constant. What if I have to divide by a number other than 2 or power of two? Returning to the division obviously, you could ask:
More generally when we represent a base number B a shifting to the right of a position corresponds to a division for B, shifting left corresponds to the corresponding multiplication for B. In binary representation, shifting to the right of a position corresponds to a division by two, as in a decimal representation a shifting to the right corresponds to a division by 10. If we have to divide by 2 or power of two, the implementation is simply shifting to the right of the number to divide. Figure 1 – division of two floating-point numbers Generally, the deployment of the division requires a much more complex logic circuit, and for this reason, we tend to avoid, where possible, the use of the division operator unless there are special cases. The example shows the use of multiplication and addition primitives. In VHDL there are the math primitive subtraction, addiction, and multiplication that are generally available in the libraries provided by the FPGA or ASIC vendor.įor example, in this post, we saw how to implement a pipelined multiplier. VHDL integer division should be really avoided?
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